I design hardware that makes computation faster.
I'm Saed Thaher. I build processors, FPGA systems and digital integrated circuits, from the instruction set down to timing closure, and I like the part where the design meets the measurement.
Six projects, in the order I built them.
Each one has its own page with the architecture, the numbers and the decisions behind them. Several figures are interactive.
From an instruction set to a routed design.
My work spans the stack between architecture and silicon. I'm most useful where a design decision has to be justified with a measurement.
- 01
RTL and digital design
Pipelines, datapaths, state machines and interfaces in SystemVerilog, Verilog and Minispec. Cycle-accurate thinking about latency and alignment.
- 02
Computer architecture
Pipelining, caches, hazards and bypassing, and instruction-set extensions judged by cycles, clock period and area together.
- 03
FPGA systems
Clocking, clock-domain crossings, memories, video and serial protocols; Vivado and Vitis through to timing closure on the board.
- 04
Verification
Testbench-driven RTL verification with golden models, randomized vectors and waveform debugging; Python models to predict results before hardware exists.
- 05
Digital IC flow
Schematic and layout, DRC and LVS, synthesis and place-and-route; power and timing trade-offs at the circuit level.
- 06
Bring-up and debugging
Getting a platform from a dead accelerator to a working one: boot flows, device trees, register-level diagnosis and controlled experiments.
Experience
Undergraduate Researcher, MIT STAR Lab
On-board compute for the BeaverCube-2 CubeSat: Versal AI Edge platform, clocking and reset, and a neural-network accelerator.
FPGA Engineering Intern, A*STAR Institute of Microelectronics
Singapore. Bubble-error correction for a high-resolution time-to-digital converter: model, RTL, synthesis.
Lab Assistant, MIT EECS (6.101)
Office hours and debugging sessions for 100+ students in Fundamentals of Programming.
Research Intern, UCLouvain
Belgium. Coupled thermal-electrical COMSOL model of heat dissipation in a power-electronics test setup.
Skills
Design and verification
Tools
Programming
Lab
Languages
Looking for a Summer 2027 internship
in digital design, FPGA or architecture.
The fastest way to reach me is email.