Digital integrated circuits, from a single transistor to a system-on-chip.
A graduate course that walks the whole digital IC flow in a modern process: four problem sets that each go one level up the stack, and a final project that takes a RISC-V system-on-chip from RTL to a physically verified layout. The process details are under a confidentiality agreement, so this page describes the work rather than the numbers.
Five steps, each one layer of abstraction higher.
Transistors, gates and layout
Sizing and simulating inverters, NAND and NOR gates and a ring oscillator, then drawing them: custom layout, design-rule and layout-versus-schematic checks, parasitic extraction, and post-layout simulation to see what the wires cost.
Arithmetic and the digital flow
Adders, multipliers, a retimed dot product and multiply-accumulate architectures, written in RTL and pushed through synthesis and place-and-route to compare them on timing, area and energy.
Power
Where the energy goes and how to stop spending it: data ordering, data gating against clock gating, parallelism traded for a lower supply voltage, and memory macros against flip-flop arrays for buffering.
A RISC-V system-on-chip, RTL to layout
Taking an open-source RV32 core and its peripherals through synthesis with and without clock gating, place-and-route, and sign-off checks, plus an open design challenge ranked on a class leaderboard.
What it adds
My other projects stop at RTL or an FPGA bitstream. This is the layer underneath: why a gate has the delay it has, and what a synthesis report is really summarizing.
Skills in use
Schematic capture and SPICE-level simulation, custom layout, physical verification, constraint-driven synthesis, place-and-route, and power analysis from switching activity.
Why no numbers
The course uses a commercial process design kit under a non-disclosure agreement. I'm glad to talk through methods and trade-offs in conversation.